This invention relates generally to flash EEPROM (Electrically Erasable and Programmable Read Only Memory) systems, and, more specifically, to memory arrays of flash EEPROM cells that individually contain two floating gates and to systems that utilize them.
There are many commercially successful non-volatile memory products being used today, particularly in the form of small cards, which use a flash EEPROM array of cells having a xe2x80x9csplit-channelxe2x80x9d between source and drain diffusions. The floating gate of the cell is positioned over one portion of the channel and the word line (also referred to as a control gate) is positioned over the other channel portion as well as the floating gate. This effectively forms a cell with two transistors in series, one (the memory transistor) with a combination of the amount of charge on the floating gate and the voltage on the word line controlling the amount of current that can flow through its portion of the channel, and the other (the select transistor) having the word line alone serving as its gate. The word line extends over a row of floating gates. Examples of such cells, their uses in memory systems and methods of manufacturing them are given in U.S. Pat. Nos. 5,070,032, 5,095,344, 5,315,541, 5,343,063, and 5,661,053, and in copending U.S. patent application Ser. No. 09/239,073, filed Jan. 27, 1999, which patents and application are incorporated herein by this reference.
A modification of this split-channel flash EEPROM cell adds a steering gate positioned between the floating gate and the word line. Each steering gate of an array extends over one column of floating gates, perpendicular to the word line. The effect is relieve the word line from having to perform two functions at the same time when reading or programming a selected cell. Those two functions are (1) to serve as a gate of a select transistor, thus requiring a proper voltage to turn the select transistor on and off, and (2) to drive the voltage of the floating gate to a desired level through an electric field (capacitive) coupling between the word line and the floating gate. It is often difficult to perform both of these functions in an optimum manner with a single voltage. With the addition of the steering gate, the word line need only perform function (1), while the added steering gate performs function (2). The use of steering gates in a flash EEPROM array is described in U.S. Pat. No. 5,313,421, which patent is incorporated herein by this reference.
In either of the two types of memory cell arrays described above, the floating gate of a cell is programmed by injecting electrons from the substrate to the floating gate. This is accomplished by having the proper doping in the channel region and applying the proper voltages to the source, drain and remaining gate(s). So called xe2x80x9csource sidexe2x80x9d injection is preferred, being described in the foregoing U.S. Pat. No. 5,313,421.
Two techniques of removing charge from floating gates to erase memory cells are used in both of the two types of memory cell arrays described above. One is to erase to the substrate by applying appropriate voltages to the source, drain and other gate(s) that cause electrons to tunnel through a portion of a dielectric layer between the floating gate and the substrate. The other erase technique is to transfer electrons from the floating gate to another gate through a tunnel dielectric layer positioned between them. In the first type of cell described above, a third erase gate is provided for that purpose. In the second type of cell described above, which already has three gates because of the use of a steering gate, the floating gate is erased to the word line, without the necessity to add a fourth gate. Although this later technique adds back a second function to be performed by the word line, these functions are performed at different times, thus avoiding the necessity of making a compromise because of the two functions. When either erase technique is utilized, a large number of memory cells are grouped together for simultaneously erasure, in a xe2x80x9cflash.xe2x80x9d In one approach, the group includes enough memory cells to store the amount of user data stored in a disk sector, namely 512 bytes, plus some overhead data. In another approach, each group contains enough cells to hold several thousand bytes of user data, equal to many disk sector""s worth of data. Multi-block erasure, defect management and other flash EEPROM system features are described in U.S. Pat. No. 5,297,148, which patent is incorporated herein by this reference.
As in most all integrated circuit applications, the pressure to shrink the silicon substrate area required to implement some integrated circuit function also exists with flash EEPROM systems. It is continually desired increase the amount of digital data that can be stored in a given area of a silicon substrate, in order to increase the storage capacity of a given size memory card and other types packages, or to both increase capacity and decrease size. One way to increase the storage density of data is to store more than one bit of data per memory cell. This is accomplished by dividing a window of a floating gate charge level voltage range into more than two states. The use of four such states allows each cell to store two bits of data, eight states stores three bits of data per cell, and so on. A multiple state flash EEPROM structure and operation is described in U.S. Pat. Nos. 5,043,940 and 5,172,338, which patents are incorporated herein by this reference.
Increased data density can also be achieved by reducing the physical size of the memory cells and/or the overall array. Shrinking the size of integrated circuits is commonly performed for all types of circuits as processing techniques improve over time to permit implementing smaller feature sizes. But there are usually limits of how far a given circuit layout can be shrunk in this manner since there is often at least one feature that is limited as to how much it can be shrunk, thus limiting the amount that the overall layout can be shrunk. When this happens, designers will turn to a new or different layout or architecture of the circuit being implemented in order to reduce the amount of silicon area required to perform its functions. The shrinking of the above-described flash EEPROM integrated circuit systems can reach similar limits.
Therefore, in order to further increase data storage density, a flash EEPROM system using a dual floating gate memory cell is being utilized along with the storage of multiple states on each floating gate. In this type of cell, two floating gates are included over its channel between source and drain diffusions with a select transistor in between them. A steering gate is included along each column of floating gates and a word line is provided thereover along each row of floating gates. When accessing a given floating gate for reading or programming, the steering gate over the other floating gate of the cell containing the floating gate of interest is raised high to turn on the channel under the other floating gate no matter what charge level exists on it. This effectively eliminates the other floating gate as a factor in reading or programming the floating gate of interest in the same memory cell. For example, the amount of current flowing through the cell, which can be used to read its state, is then a function of the amount of charge on the floating gate of interest but not of the other floating gate in the same cell. This cell array architecture and operating techniques are described in U.S. Pat. No. 5,712,180 and copending application Ser. No. 08/910,947, filed Aug. 7, 1997, which patent and application are incorporated herein by this reference.
Therefore, it is among primary objects of the present invention to provide a dual floating gate memory cell array that permits increased density data storage and the downward scaling of its size.
It is another object of the present invention to provide improved operating techniques for memory systems including flash EEPROM cell arrays, including those of the dual floating gate type.
It is a further object of the present invention to provide improved processing techniques for forming flash EEPROM cell arrays, including those of the dual floating gate type.
These and additional objects are accomplished by the present invention, wherein, briefly and generally, according to one aspect, an array of dual floating gate flash EEPROM cells have steering gates with widths that extend over and are capacitively coupled with two adjacent floating gates of adjacent memory cells in a row. This reduces the number of steering gates by one-half and, in an embodiment where the floating gates are formed on the surface of the substrate, increases their individual widths by more than twice since they also extend over a source or drain diffusion that is positioned between the adjacent cells. The wider steering gate allows it to be formed more easily, need not be the minimum resolvable feature size, provides an increased level of conduction along its length, thus, when made of polysilicon material, reducing the number of contacts that must be made to it from metal conductors, and the making of those contacts becomes easier.
According to another aspect of the present invention, floating gates are positioned along walls of trenches formed in the surface of the substrate, source and drain diffusions are provided at the bottom of the trenches, and the select transistor between the two floating gates of individual cells is formed on the surface of the substrate. The steering gate common to the floating gates in a particular trench is formed between them in the same trench, thus being oriented in cross-section in a direction that is orthogonal to the surface of the substrate. This structure has the added advantage of further reducing the area of the substrate taken by a single cell. The ability to share the steering gate between adjacent floating gates of two memory cells on opposite sides of a source or drain diffusion makes this trench configuration practical.
Additional objects, advantages and features of the present invention are included in the following description of its preferred embodiments, which description should be taken in conjunction with the accompany drawings. Specifically, improved techniques of forming and of operating flash EEPROM cell arrays and systems are included as part of the present invention, as applied to the dual gate memory cell embodiments specifically described herein and more generally to other dual gate cell structures and memory arrays having other than the dual gate cell configuration.